A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis for

Data Transmission over 75 Coaxial Cable

Ricardo A. Aroca & Sorin P. Voinigescu

Edward S. Rogers, Sr. Dept. of Electrical & Comp. Eng.,University of Toronto, Toronto, ON M5S 3G4, Canada

2

OutlineOutline

Motivation

Driver Specifications

Driver Architecture and Design

Measurements

Transmission Experiment

Conclusions

3

MotivationMotivation

Transport 40-Gb/s over existing coaxial cable infrastructure

Transceiver IC must be low-cost, highly integrated, and capable

of equalizing up to 50dB of channel losses

Belden 1694A

TX/RXIC

4

Transceiver ArchitectureTransceiver Architecture

Line driver

Transmitserializer

and40-G PLL

40-GHzclock

40 Gb/s @ 1 – 1.8V

40 Gb/s@ 5V

DFEFFE

TimingRecovery

40-GHzclock

Line driver

• Focus on the TX, RX in development

• TX requires amplitude control and pre-emphasis control

• Place as much equalization into the TX to ease the RX specs

5

40-Gb/s, 7540-Gb/s, 75 Driver Specifications Driver Specifications

Parameter SpecificationInput DC level 1 - 1.8V

Min Input Amplitude 200mVpp

Output Swing: driving 75 driving 50

1 – 5Vpp per side

0.8 – 4Vpp per side

Gain: > 28dB

> 26dB

Bandwidth: > 20GHz

> 25GHz

S11, S22 < -10dB up to 40GHz

Duty Cycle 30 - 70%

Pre-Emphasis 0 - 400%

PDC ~3W

CMOS

6

Production TechnologyProduction Technology Jazz HX 0.2 Jazz HX 0.2m SiGe BiCMOSm SiGe BiCMOS

0.18m n-MOSFET

fMAX = 75GHz

fT = 50GHz

JpkfT = 0.3mA/m NMOS

HV-HBT

HV-HBT, BVceo=3.5V

fMAX = 100GHz

fT = 75GHz

JpkfT = 2.5mA/m2

7

Distributed Architecture DesignDistributed Architecture Design

Amp & Pre-Emphasis

Itail CNTRL

DCC

AMP

8V

8V75

75

OUTP

OUTN

1 2 3 4 5 6 7

5V

75

8V

8V

7575 Microstrip T-Line Sections

Pre-Driver

INP

INN

• IOUT = 5Vpp/(75//75) = 133mA 19mA/section

• Must fully switch the DA predriver: 1.5Vpp, 40mA

• Gain of predriver = 1.5/0.2 = 18dB, 3dB/stage 6 stages

• Distributed pre-emphasis is implemented for the first time

• Amplitude control is implemented in both the DA and predriver

8

C

R

C

RIMAIN

IPRE

IOFF

VPRE VPRE

~5V ~5VT-line section T-line compensation

DA Section SchematicDA Section Schematic

0.18m n-MOSFETs fT=50GHz, fMAX=75GHz

HV-HBTfT=75GHzfMAX=100GHz

RC-HPF & Digital HBT fT=160GHz, fMAX=160GHz

9

C

R

C

RIMAIN

IPRE

IOFF

VPRE VPRE

~5V ~5VT-line section T-line compensation

DA Section SchematicDA Section Schematic

IT=IMAIN+IPRE

IT

• IT is variable, for amplitude control at different pre-emphasis settings

• IOFF adjusts to ensure current through HV-HBT is constant

10

Driver MicrophotographDriver Microphotograph

Distributed Amplifier

Predriver

2.5mm

1.2mm

11

S-parameter Measurements vs. S-parameter Measurements vs. Simulations: 10dB of Amplitude ControlSimulations: 10dB of Amplitude Control

22GHz10dB

12

S-Parameter Measurements vs. S-Parameter Measurements vs. Simulations: 25dB of Pre-Emphasis ControlSimulations: 25dB of Pre-Emphasis Control

25dB

13

40-Gb/s Eyes @ 2540-Gb/s Eyes @ 25ooC and 125C and 125ooCC

3Vpp 1Vpp

25oC

• Input: 200mVpp, 4x(231-1 PRBS)

• 2ps RMS jitter (1khits)

• ~11ps rise/fall times1.9Vpp

125oC

14

40-Gb/s Pre-Emphasis @ 2540-Gb/s Pre-Emphasis @ 25ooC and 125C and 125ooCC

125oC

1.3Vpp

• Input: 200mVpp, 4x(231-1 PRBS)

• 200-400% pre-emphasis

1Vpp 2Vpp

25oC

15

Maximum Output Amplitude @ 38Gb/s Maximum Output Amplitude @ 38Gb/s

3.6Vpp per side in a 50 load, 10.5ps rise time, 2.2ps RMS jitter (1.17khits)

16

40-Gb/s Driver Performance in 5040-Gb/s Driver Performance in 50Parameter Target Measured

Input DC level 1 - 1.8V 1 - 1.8V

Min Input Amplitude 200mVpp 200mVpp

Output Swing: driving 75 driving 50

1 – 5Vpp per side

0.8 – 4Vpp per side 0.8 - 3.6Vpp per side

Gain: driving 75 driving 50

> 28dB

> 26dB 36dB

Bandwidth > 20GHz

> 25GHz 22GHz

S11, S22 (up to 40GHz) < -10dB < -10dB

Duty Cycle 30 - 70% 35 – 65%

Pre-Emphasis 0 - 400% 0 - 400%

PDC ~3W 3.6W

17

40-Gb/s, 5040-Gb/s, 50 Driver Comparison Driver Comparison

Parameter GaAs [1]

InP [3] SiGe [2]

This Work

fT / fMAX (GHz) 100 / 200 150 / 200 120 / 160MOS: 50 / 75HV-HBT: 75 / 100

Topology LD* LD LD LD

Swing (per side) 1.7 - 3 1 - 5.65 3.4 0.8 - 3.6

Gain (dB) 16 30 - 36

Bandwidth (GHz) - 45 - 22

Duty Cycle (%) 30 – 70 - - 35 – 65

PDC (W) 2.8 3 < 3 3.6

Pre-Emphasis no no no 0 - 400%

*LD – Lumped predriver followed by a distributed amplifier

*[ ] – Reference numbers refer to those cited in the paper

18

Transmission Experiment over 10m, 30m Transmission Experiment over 10m, 30m and 40m of Belden Coaxial Cableand 40m of Belden Coaxial Cable

RSH

To Remote Sampling Head (RSH)

Source

BIAS

BIAS

10m,30m,40m coax

INPUT TO CHANNEL

AFTER CHANNEL

K-SMA-BNC

T

RSHT

4x231-1 PRBS

19

Equalized Channel ResponseEqualized Channel Response

Range of all possible equalized channel responses

INPUT TO CHANNELCHANNEL

AFTER CHANNEL

20

10-Gb/s over 40m Coax10-Gb/s over 40m Coax

-24dB

50mVpp

No Pre-emphasis With Pre-emphasis

21

40- & 38-Gb/s over 10m Coax40- & 38-Gb/s over 10m Coax

-23dB

200mVpp

Pre-emphasis @40Gb/s Pre-emphasis @38Gb/s

No Pre-emphasis

200mVpp

22

ConclusionsConclusions

Large swing, fully-differential 40-Gb/s SiGe BiCMOS

cable driver with adjustable pre-emphasis has been

presented.

Key features include:

Distributed pre-emphasis technique

MOS-HV-HBT cascode topology

Transmission experiments over Belden 1694A coax:

equalization of -24dB of loss at 5GHz

equalization of -22dB at 19GHz

Experimental results indicate that this driver could also

be used as a 50 EAM driver operating at 40 Gb/s.

23

AcknowledgementsAcknowledgements

Jazz Semiconductor and Marco Racanelli for fabrication

Gennum Corporation and NSERC for funding

Jaro Pristupa for CAD support

24

Backup SlidesBackup Slides

25

Transmission Experiment over 10m, 30m Transmission Experiment over 10m, 30m and 40m of Belden Coaxial Cableand 40m of Belden Coaxial Cable

Source

RSH

RSH

To Remote Sampling Head (RSH)

DUT

Coax

26

38- & 30-Gb/s over 10m Coax Cable38- & 30-Gb/s over 10m Coax Cable

-17.7dB

30-Gb/s

27

20-Gb/s over 30m Coax Cable20-Gb/s over 30m Coax Cable

-29dB

28

Measurement BottlenecksMeasurement Bottlenecks

1. 75 cable driver to be measured in a 50 environment

Eventual packaging will solve this problem

2. How will S21 and S22 change when driving a 75 load

when compared to the 50 measurement?

S21 and S22 will improve in theory

3. How can we verify the maximum swing to be expected

in a 75 environment?

Theoretically the swing driving 75 should be 1.25 times the

swing driving 50

29

Driver Output Impedance: Driver Output Impedance: Measurements vs. SimulationsMeasurements vs. Simulations

30

DCC Control @ 40- and 30-Gb/sDCC Control @ 40- and 30-Gb/s

31

Choice of TechnologyChoice of Technology

CMOS 90/65nm

SiGe BiCMOS

III-V

System Integration

Output swing (5Vpp per side)

High-speed (40Gb/s)

SiGe BiCMOS is the best optionSiGe BiCMOS is the best option

Considerations

Low cost ?

Reliability over temperature ?

T. Chalvatzis, JSSC07

40-Gb/s Retimer in 90nm CMOS – need 65nm for margin

32

Initial Driver DesignInitial Driver DesignDriving a 75 coax cable with 5Vpp per side requires digital switching of ~133mA

For reliable operation under large output voltage swings, high voltage HBTs (HV-HBT) are required at

the output node

BVCEO=3.5V

fT = 75GHz

fMAX = 100GHz

RC time constant analysis, when the HV-HBT is biased at 0.75*JpkfT, results in a -3dB bandwidth of

~10GHz,

Lumped toplogy is not an option therefore pointing to a distributed architecture (at least for the output

stage)

IT = 5Vpp / 37.5

= 133mALine driver

Vdd

75

Vdd

75Vdd

75

Vdd

75

33

~3.3V

~3.3V

DCC current

~3.3V

~3.3V

10mA

~3.3V

1.1 - 1.8V

60

600

Small Input Device to minimize capacitance and improve input matching without EFs

3mA

50

50

INP

INN

Lumped Predriver ArchitectureLumped Predriver Architecture

Amplitude Control

Offset Control

400mV

10mA

800mV

20mA

1V

40mA

1.2V

DCC

5mA 5mA

300mV

Output Swing per side:

Input DC 1.1V - 1.8V

BiCMOS cascode used in the final two stages for stability

Topology is ideal for impelmenting amplitude control

Vdd

75

Vdd

75

34

40mA Output Stage40mA Output Stage

8 x 5.46m Digital

8 x 5.46m HV-HBT

2m x 66L=0.18m

~5V

~3.3V~3.3V

75 75

35

T-line section

T-Line CompensationT-Line Compensation

• Distributed T-line inductors designed to absorb the load capacitance from the DA stage

• minimize the impact on Z0, S21, and phase distortion