Lab2_Conexiuni_Ierarhice

8/23/2019 Lab2_Conexiuni_Ierarhice

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Laborator 2

Hierarchical Connections in Verilog

Necessary Hardware and Software

- Nexys2 Development Boards + USB-Mini Cable USB-Mini- ISE 12.2 or newer software

Laboratory work

1. Half-adderSchematics:

Figure 1. Half-Adder schematic

a. Create a new project on C:\Temp targeting the FPGA device present on thedevelopment board you have. Name the project HalfAdders_group_name, where

group_name is the name of the group and halfgroup where do you belong, for

example 2142_2

a. Create a new Verilog module with the 1-bit inputs A and B, outputs C and S. Namethe Verilog module HA. Write the body of the Verilog code.

b. Using the UCF constraints, connect A to SW0, B to SW4, S to LED0 and C to LED4.Implement the design and download it to the development board. Check the design

on the board for functionality.

2. One-bit Full AdderSchematics:


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Note that the full adder schematic can be built of two half-adders:

Figure 2. One bit Full-Adder schematic

a. Create a new project on C:\Temp targeting the FPGA device present on thedevelopment board you have. Name the project Full_Adder_1_bit_group_name,

where group_name is the name of the group and halfgroup where do you belong,

for example 2142_2

b. First create the top-level module. Name it fulladd. Create its ports, using thefollowing algorithm:

Figure 3. One bit Full-Adder top level ports


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c. Then create the internal signals:

Figure 4. One bit Full-Adder internal signals

d. From the Project Navigator window right-click on the top-level module and chooseAdd Copy of Source. Navigate to the previously created HA module and add it

to the project.

e. Create the internal connections by writing into the Verilog module body, in thefollowing way:

Figure 5. One-bit Full-Adder internal connections


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Note: Assuming that HA was defined in the following way:

module HA

( input A,

input B,

output Soutput C

);

Then, the HA_0 instance of HA can be connected as

HA HA_0 (A, B, S0, C0);

Also the HA_1 instance of HA can be connected as

HA HA_1 (S0, Cin, S, C1)

Note that ports can be connected to a Verilog module just by using its PORT ORDER,

i.e. the order in which its ports have been DEFINED.

f. Assign Cin to SW0. Assign A to SW1, B to SW2. Assign S to Led0 and C to Led1.Implement the design on the board and try the designs functionality on the board.

3. Two-bit Full AdderSchematics:

fulladdB

A S

C

A[1:0]

B[1:0]

Cin

C0

FA_0

Cin

fulladdB

A S

C

FA_1

Cin

2

2

S[0]

S[1]

C

A[1]

B[1]

A[0]

B[0]

Figure 6. Two bit Full-Adder schematics

a. Create a new project on C:\Temp targeting the FPGA device present on thedevelopment board you have. Name the project Full_Adder_2_bit_group_name,


for example 2142_2


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b. Create a new top-level module with its ports according to Figure 6. Name the top-level module Full_Adder_2_bit.

c. From the Project Navigator window right-click on the top-level module and chooseAdd Copy of Source. Navigate to the previously created HA and fulladd

modules and add them to the project.d. Create the internal connections of the new module according to the schematic

shown in Figure 6.

e. Assign Cin to SW7. Assign A[1:0] to SW[1:0], B[1:0] to SW[5:4]. Assign S[1:0] toLed[1:0] and C to Led7. Implement the design on the board and try the designs

functionality on the board.

4. Four-bit-bit Full AdderSchematics:

Figure 7. Four bit Full-Adder schematics


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b. Create a new project on C:\Temp targeting the FPGA device present on thedevelopment board you have. Name the project Full_Adder_4_bit_group_name,


for example 2142_2

c.

Create a new top-level module with its ports according to Figure 7. Name the top-level module Full_Adder_4_bit.

d. From the Project Navigator window right-click on the top-level module and chooseAdd Copy of Source. Navigate to the previously created HA and fulladd

modules and add them to the project.

e. Create the internal connections of the new module according to the schematicshown in Figure 6.

f. Assign Cin to BTN0. Assign A[3:0] to SW[3:0], B[3:0] to SW[7:4]. Assign S[3:0] toLed[3:0] and C to Led7. Implement the design on the board and try the designs


5. Four-bit-bit Full Adder Implementation using Generate Statements.a. Create a new project on C:\Temp targeting the FPGA device present on the

development board you have. Name the project

Full_Adder_4_bit_generate_group_name, where group_name is the name of the

group and halfgroup where do you belong, for example 2142_2

b. Rewrite the body ow the Verilog code using generate statements. Note thatgenerate statements can be used for automating component instantiation. The

code body should look like this:

wire [3:0] Cy_int;

fulladd FA_0

(

.A (A[0]),

.B (B[0]),

.Cin (Cin),

.C (Cy_int[0]),

.S (S[0])

);


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genvar i;

generate

for (i=1; i < 4; i=i+1)

begin: FULL_ADDERS

fulladd FA_i(

.A (A[i]),

.B (B[i]),

.Cin (Cy_int[i-1]),

.C (Cy_int[i]),

.S (S[i])

);

end

endgenerate

assign C = Cy_int[3];

c. Assume that Cin is assigned to BTN0. Assign A[3:0] to SW[3:0], B[3:0] to SW[7:4].Assign S[3:0] to Led[3:0] and C to Led7. Implement the design on the board and try

the designs functionality on the board.

6. Four-bit-bit Full Adder Implementation using the Seven-Segment displaya. Create a new project on C:\Temp targeting the FPGA device present on the

development board you have. Name the project

Full_Adder_4_bit_ssg_group_name, where group_name is the name of the group

and halfgroup where do you belong, for example 2142_2

b. Copy the source named Ssg_decoder.v (for example, by using the Add Copy ofSource command), into your current project. Create the main module according to

the schematic in Figure 8.

c. Using the previously created project, make a component named fulladd_4 and copyits sources into your current project

d. Create a Verilog moduel and call it Main. Make the schematics connectionsaccording to Figure 8.

Schematics:


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Figure 8. Four bit Full-Adder with results displayed on the 7-segment display

e. Assign the projects input and output ports according to the schematic in Figure 8.Connect the CLK signal to where is specified in the ucf file (B8). Test the designs


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