An2 Derivat.ro Arhitectura-microprocesoarelor AMP Lab3 Eng 36298

7/30/2019 An2 Derivat.ro Arhitectura-microprocesoarelor AMP Lab3 Eng 36298

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Politehnica University of Bucharest Microprocessors Architecture Lab guide

Electronics, Telecommunications and Information Technology Faculty Paper 3

Corneliu Burileanu

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Data processing instructions and

program control instructions for Intel

x86 (IA-32) and compatible processors

1. Papers purposeThis papers purpose is to get you familiar with the data processing instructions and program control

instructions of Intel x86 and compatible processors.

2. Instruction summary

We convene upon the same notations as in Laboratory 2. Please pay special attention to the way flags

are being modified by the instructions presented in this paper!

2.1 Arithmetic instructions

Increment OF DF IF TF SF ZF AF PF CFINC d destination x x x x x

General formal semantic description: (d) (d) + 1.

Operands Examples Formal semantic description

r16 INC BX (BX) (BX) + 1

r8 INC AL (AL) (AL) + 1

mem INC [BP+DI] ((SS)0H + (BP) + (DI))

((SS)0H + (BP) + (DI)) + 1

ASCII adjustment OF DF IF TF SF ZF AF PF CFAAA for addition ? ? ? x ? x

Formal semantic description: if (AL) & 0F > 9 or (AF) = 1 then

(AL) (AL) + 6

(AH) (AH) + 1

(AF) 1

(CF) (AF)

(AL)

(AL) & 0F.

Decimal adjustment OF DF IF TF SF ZF AF PF CFDAA for addition ? x x x x x


(AL) (AL) + 06H

(AF) 1

if (AL) > 9F or (CF) = 1 then

(AL) (AL) + 60H


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OF DF IF TF SF ZF AF PF CFADD d,s Add source with x x x x x x

destination

General formal semantic description: (d) (d) + (s).

Operands Examples Formal semantic descriptionAL|AX, data ADD AL,33H (AL) (AL) + 33H

r, data ADD CH,10H (CH) (CH) + 10H

mem, data ADD [BP],ALFA ((SS)0H+(BP))((SS)0H+(BP)) + ALFAr1, r2 ADD CL,CH (CL) (CL) + (CH)

r, mem ADD SI,[SI+22H] (SI) (SI) + ((DS)0H + (SI) + 23H)

((DS)0H + (SI) + 22H )

mem, r ADD [BX],BX ((DS)0H+(BX)+1)((DS)0H+(BX)) ((DS)0H+(BX)+1)((DS)0H+(BX)) + (BX)

Add source with OF DF IF TF SF ZF AF PF CF

ADC d,s destination and x x x x x x

carry

General formal semantic description: (d) (d) + (s) + (CF).


AL|AX, data ADC AL,15H (AL)(AL) + 15H + (CF)r, data ADC BX,0100H (BX)(BX) + 100H + (CF)mem, data ADC [DI],1234H ((DS)0H+(DI)+1)((DS)0H+(DI))

((DS)0H+(DI)+1)((DS)0H+(DI)) +1234H+(CF)r1, r2 ADC AX,DI (AX) (AX) + (DI) + (CF)

r, mem ADC DX,[BX] (DX) (DX) +((DS)0H + (BX) + 1)

((DS)0H + (BX)) + (CF)

mem, r ADC [BX+DI+12H],DX ((DS)0H + (BX) + (DI) + 13H) ((DS)0H + (BX) + (DI) +12H)

((DS)0H + (BX) + (DI) + 13H)

((DS)0H + (BX) + (DI) +12H) +

+ (DX) + (CF)


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OF DF IF TF SF ZF AF PF CFSUB d,s Subtract x x x x x x

General formal semantic description: (d) (d) - (s).Operands Examples Formal semantic description

AL|AX, data SUB AL,20H (AL) (AL) - 20H

r, data SUB BX,5566H (BX) (BX) - 5566Hmem, data SUB [BP+25H],444H ((SS)0H+(BP)+26H) ((SS)0H+(BP)+25H)

((SS)0H+(BP)+26H)

((SS)0H+(BP)+25H) - 0444Hr1, r2 SUB DX,DI (DX) (DX) - (DI)r, mem SUB SI,[BX+100H] (SI) (SI) - ((DS)0H + (BX) + 101H)

((DS)0H + (BX) + 100H)

mem, r SUB [BP+50H],AX ((SS)0H + (BP) + 51H)

((SS)0H + (BP) + 50H)

((SS)0H + (BP) + 51H) ((SS)0H + (BP) + 50H) - (AX)

OF DF IF TF SF ZF AF PF CFSBB d,s Subtract with x x x x x x

borrow

General formal semantic description: (d) (d) - (s) - (CF).Operands Examples Formal semantic description

AL|AX, data SBB AX,1000H (AX) (AX) - 1000H - (CF)

r, data SBB DI,23H (DI)

(DI) - 0023H - (CF)mem, data SBB [BX+DI],33H ((DS)0H+(BX)+(DI)) ((DS)0H+(BX)+(DI))-

- 33H - (CF)

r1, r2 SBB AL,BL (AL) (AL) - (BL) - (CF)r, mem SBB AH,[DI+55H] (AH) (AH) - ((DS)0H + (DI) + 55H) - (CF)mem, r SBB [BX],DL ((DS)0H + (BX)) ((DS)0H + (BX)) -

- (DL) - (CF)

Decrement OF DF IF TF SF ZF AF PF CFDEC d destination x x x x x

General formal semantic description: (d) (d) - 1.Operands Examples Formal semantic description

r16 DEC AX (AX) (AX) 1

r8 DEC DH (DH) (DH) 1

mem DEC [BP+12H] ((SS)0H + (BP) + 12H)

((SS)0H + (BP) + 12H) - 1


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Negate source OF DF IF TF SF ZF AF PF CFNEG d (2s complement) x x x x x 1*

General formal semantic description: (d) 0H - (d).

Operands Examples Formal semantic descriptionr NEG AX (AX) 0H - (AX)

mem NEG [DI] ((DS)0H + (DI)) 0H - ((DS)0H + (DI))* (CF) = 0 if (d) = 0H

OF DF IF TF SF ZF AF PF CF

CMP s1,s2 Compare operands x x x x x x

General formal semantic description: (s1) - (s2).

Operands Examples Formal semantic descriptionAL|AX, data CMP AX,0FFFFH (AX) - FFFFH

r, data CMP BX,10H (BX) - 0010H

mem, data CMP [BP+SI+5H],0ABH ((SS)0H + (BP) + (SI) + 5H) - ABH

r1, r2 CMP AL,CL (AL) - (CL)

r, mem CMP BH,[100H] (BH) - ((DS)0H + 100H)

mem, r CMP [BX+SI+45H],DX ((DS)0H + (BX) + (SI) + 46H) ((DS)0H + (BX) + (SI) + 45H) - (DX)

ASCII adjustment OF DF IF TF SF ZF AF PF CFAAS for subtraction ? ? ? x ? x


(AL) (AL) - 6, (AH) (AH) - 1

(AF) 1

(CF) (AF)

(AL) (AL) & 0F.

Decimal adjustment OF DF IF TF SF ZF AF PF CFDAS for subtraction ? x x x x x


(AL) (AL) - 06H

(AF) 1

if (AL) > 9F or (CF) = 1 then

(AL) (AL) - 60H

(CF) 1


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OF DF IF TF SF ZF AF PF CFMUL s Multiplication x ? ? ? ? x

General formal semantic description:

for the 8 bit operation:

(AX) (AL) * (s) if (AH) = 0 then(CF) 0

else (CF) 1(OF) (CF) ,

for the 16 bit operation:(DX)(AX) (AX) * (s) if (DX) = 0 then

(CF) 0else (CF) 1

(OF) (CF).Operands Examples Formal semantic description

r8 MUL DL (AX) (AL) * (DL)

r16 MUL BX (DX)(AX) (AX) * (BX)

mem8 MUL [BP+DI] (AX) (AL) * ((SS)0H + (BP) + (DI))

mem16 MUL [1268H] (DX)(AX) (AX) * ((DS)0H + 1269H)

((DS)0H + 1268H)

Signed integer OF DF IF TF SF ZF AF PF CFIMUL s multiplication x ? ? ? ? x


for the 8 bit operation:(AX) (AL) * (s)if (AH) = 0 or (AH) = FF then

(CF) 0

else (CF) 1

(OF) (CF) ,

for the 16 bit operation:(DX)(AX) (AX) * (s)

if (DX) = 0 or (DX) = FFFF then

(CF) 0

else (CF) 1

(OF) (CF).


r8 IMUL DL (AX) (AL) * (DL)

r16 IMUL CX (DX)(AX)(AX) * (CX)mem8 IMUL [0ABCDH] (AX) (AL) * ((DS)0H + ABCDH)

mem16 IMUL [BX+550H] (DX)(AX) (AX) * ((DS)0H+(BX)+551H) ((DS)0H+(BX)+550H)


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ASCII adjustment OF DF IF TF SF ZF AF PF CFAAM for multiplication ? x x ? x ?

(done after the

multiplication)

Formal semantic description: (AH) (AL) div 0A

(AL) (AL) mod 0A.

OF DF IF TF SF ZF AF PF CFDIV s Division ? ? ? ? ? ?

General formal semantic description: for the 8 bit operation:

if (AX) div (s) > FF then

(SP) (SP) - 2

((SS)0H + (SP) + 1) ((SS)0H + (SP)) (F)

(IF) 0

(TF) 0

(SP) (SP) - 2((SS)0H + (SP) + 1) ((SS)0H + (SP)) (CS)

(CS) (00003H) (00002H)

(SP) (SP) - 2

((SS)0H + (SP) + 1) ((SS)0H + (SP)) (IP)

(IP) (00001H) (00000H)

else (AL) (AX) div (s)

(AH) (AX) mod (s),

for the 16 bit operation:

if (DX)(AX) div (s) > FFFF then

(SP) (SP) - 2

((SS)0H + (SP) + 1) ((SS)0H + (SP)) (F)

(IF) 0

(TF) 0

(SP) (SP) - 2

((SS)0H + (SP) + 1) ((SS)0H + (SP)) (CS)

(CS) (00003H) (00002H)(SP) (SP) - 2

((SS)0H + (SP) + 1) ((SS)0H + (SP)) (IP)

(IP) (00001H) (00000H)

else (AX) (DX)(AX) div (s)

(DX) (DX)(AX) mod (s) .


r8 DIV CL (AL) (AX) div (CL)

(AH) (AX) mod (CL)r16 DIV BX (AX) (DX)(AX) div (BX)

(DX) (DX)(AX) mod (BX)mem8 DIV [BP+50H] (AL) (AX) div ((SS)0H + (BP) + 50H)

(AH) (AX) mod ((SS)0H + (BP) + 50H)mem16 DIV [DI+41H] (AX) (DX)(AX) div ((DS)0H+(DI)+42H)

((DS)0H+(DI)+41H)

(DX)(DX)(AX) mod ((DS)0H+(DI)+42H)

((DS)0H+(DI)+41H)


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Signed integer OF DF IF TF SF ZF AF PF CFIDIV s division ? ? ? ? ? ?

The formal semantic description is similar with the one presented for the previous instruction. One exceptionoccurs: the initial comparison for signed inegers is:

for the 8 bit division:

if (AX) div (s) > 0 and (AX) div (s) > FF or(AX) div (s) < 0 and (AX) div (s) < 0-FF-1 then ... ,

for the 16 bit division:

if (DX)(AX) div (s) > 0 and (DX)(AX) div (s) > FFFF or

(DX)(AX) div (s) < 0 and (DX)(AX) div (s) < 0-FFFF-1 then ...


r8 DIV BL (AL) (AX) div (BL)

(AH) (AX) mod (BL)r16 DIV CX (AX) (DX)(AX) div (CX)

(DX) (DX)(AX) mod (CX)mem8 DIV [BX+SI] (AL) (AX) div ((DS)0H + (BX) + (SI))

(AH) (AX) mod ((DS)0H + (BX) + (SI))mem16 DIV [BP] (AX) (DX)(AX) div ((SS)0H +(BP) +1)

((SS)0H +(BP))

(DX) (DX)(AX) mod ((SS)0H +(BP) +1)

((SS)0H +(BP))

ASCII adjustment OF DF IF TF SF ZF AF PF CFAAD for division ? x x ? x ?

(done before the

division)

Formal semantic description: (AL) (AH) * 0AH + (AL)

(AH) 0H.

Byte to word OF DF IF TF SF ZF AF PF CFCBW conversion

(with sign)

Formal semantic description: if (AL) < 80H then

(AH) 00H

else (AH) FFH.

Word to double word OF DF IF TF SF ZF AF PF CFCWD conversion

(with sign)

Formal semantic description: if (AX) < 8000H then

(DX) 0000H

else (DX) FFFFH.


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2.2 Logical instructions

Logical NOT OF DF IF TF SF ZF AF PF CFNOT d (1s complement)


(d) FFH - (d), for an 8 bit operand, or(d) FFFFH - (d), for a 16 bit operand.


r NOT AX (AX) FFFFH - (AX)

mem NOT [0EEFFH] ((DS)0H +EEFFH) FFH -

- ((DS)0H+EEFFH)

OF DF IF TF SF ZF AF PF CFAND d,s Logical AND 0 x x ? x 0

General formal semantic description: (d) (d) & (s).Operands Examples Formal semantic description

AL|AX, data AND AX,0FFH (AX) (AX) & 0033H

r, data AND CX,10H (CX) (CX) & 0010Hmem, data AND [DI],0AAAAH ((DS)0H +(DI) +1) ((DS)0H +(DI))

((DS)0H +(DI) +1) ((DS)0H +(DI)) &

& AAAAH

r1, r2 AND CL,DL (CL) (CL) & (DL)r, mem AND DX,[BP] (DX) (DX) & ((SS)0H + (BP) + 1H)

((SS)

0H + (BP))

mem, r AND [BX+DI],CL ((DS)0H+(BX)+(DI))

((DS)0H+(BX)+(DI)) & (CL)

Test OF DF IF TF SF ZF AF PF CFTEST s1, s2 (compares the two 0 x x ? x 0

values without

storing the result)

General formal semantic description: (s1) & (s2).

Operands Examples Formal semantic descriptionAL|AX, data TEST AL,55H (AL) & 55H

r, data TEST DI,1234H (DI) & 1234H

mem, data TEST [SI],00101100B ((DS)0H + (SI)) & 00101100B

r1, r2 TEST DI,BX (DI) & (BX)

r, mem TEST CL,[SI] (CL) & ((DS)0H + (SI))


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OF DF IF TF SF ZF AF PF CFOR d,s Logical OR 0 x x ? x 0

General formal semantic description: (d) (d) (s) .

Operands Examples Formal semantic descriptionAL|AX, data OR AL,22H (AL) (AL) 22H

r, data OR DX,1FFFH (DX) (DX) 1FFFH

mem, data OR [BP+SI],1 ((SS)0H +(BP) + (SI))

((SS)0H +(BP) + (SI)) 01Hr1, r2 OR CL,BL (CL) (CL) (BL)r, mem OR BX,[SI] (BX) (BX) ((DS)0H + (SI) + 1H)

((DS)0H + (SI))

mem, r OR [BP+DI],CX ((SS)0H +(BP) +(DI) +1)

((SS)0H +(BP) +(DI))

((SS)0H +(BP) +(DI) +1)

((SS)0H +(BP) +(DI))(CX)

OF DF IF TF SF ZF AF PF CFXOR d,s Logical XOR 0 x x ? x 0

General formal semantic description: (d) (d) (s).


AL|AX, data XOR AX,333H (AX) (AX) 0333H

r, data XOR BP,245H (BP) (BP) 0245H

mem, data XOR [DI],7788H ((DS)0H +(DI) +1H) ((DS)0H +(DI))

((DS)0H +(DI) +1H) ((DS)0H +(DI)) 7788Hr1, r2 XOR DX,SI (DX) (DX) (SI)

r, mem XOR CX,[BX+SI] (CX) (CX) ((DS)0H +(BX) +(SI) +1H) ((DS)0H +(BX) +(SI))

mem, r XOR [DI+0AAH],BL ((DS)0H +(DI) +AAH)

((DS)0H +(DI) +AAH) (BL)


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2.3 Shift and rotation instructions

Shift right OF DF IF TF SF ZF AF PF CFSAL | SHL arithmetic | x x x ? x x

s, nrcel logical

Formal semantic description:

while nrcel 0 do(CF) (s)msb

(s) (s) * 2

(s)lsb 0

nrcel nrcel - 1

if nrcel = 1 then

if (s)msb (CF) then (OF) 1

else (OF) 0else (OF) undetermined.

Shift right OF DF IF TF SF ZF AF PF CFSHR s, nrcel (logical) x x x ? x x

Formal semantic description:while nrcel 0 do

(s)msb 0

(s) (s) div 2

(CF) (s)lsb

nrcel nrcel - 1

if nrcel = 1 then

if (s)msb (s)msb-1 then (OF) 1

else (OF) 0else (OF) undetermined.

Shift arithmetic OF DF IF TF SF ZF AF PF CFSAR s, nrcel right x x x ? x x

The formal semantic description is similar

to the one presented for the previousinstruction. However there are two

differences: msb is not cleared and OF is

reset even ifnrcel

1.

Operands Examples

r, 1 SHL BX,1

r, CL SAL DX,CL

mem, 1 SHL [BX+SI],1

mem, CL SHL [DI+10H],CL

Operands Examples

r, 1 SHR DL,1

r, CL SHR BX,CL

mem, 1 SHR [DI],1

mem, CL SHR [BP+SI+4H],CL

Operands Examples

r, 1 SAR BH,1

r, CL SAR AX,CL

mem, 1 SAR [BX],1

mem, CL SAR [BP+SI],CL


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OF DF IF TF SF ZF AF PF CFROL s, nrcel Rotate left x x


(s) (s) * 2(CF) (s)msb

(s)lsb (s)msb

nrcel nrcel - 1

if nrcel = 1 then

if (s)msb (CF) then (OF) 1

else (OF) 0

else (OF) undetermined.

OF DF IF TF SF ZF AF PF CFROR s, nrcel Rotate right x x


(s) (s) div 2

(s)msb (s)lsb

(CF) (s)lsb

nrcel nrcel - 1

if nrcel = 1 then

if (s)msb (s)msb-1 then (OF) 1

else (OF) 0

else (OF) undetermined.

OF DF IF TF SF ZF AF PF CFRCL s, nrcel Rotate carry left x x

The formal semantic description is similar to

the one for the rotate left instruction.

OF DF IF TF SF ZF AF PF CFRCR s,nrcel Rotate carry right x x

The formal semantic description is similar tothe one for the rotate right instruction.

Operands Examples

r, 1 ROL SI,1

r, CL ROL DX,CL

mem, 1 ROL [BX+DI],1

mem, CL ROL [BP+100H],CL

Operands Examples

r, 1 ROR AX,1

r, CL ROR DX,CL

mem, 1 ROR [BP],1

mem, CL ROR [1000H],CL

Operands Examples

r, 1 RCL CX,1

r, CL RCL AL,CL

mem, 1 RCL [SI],1

mem, CL RCL [BX+DI],CL

Operands Examples

r, 1 RCR AX,1

r, CL RCR BX,CL

mem, 1 RCR [BP+DI],1

mem, CL RCR [BX],CL


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Corneliu Burileanu

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2.4 Unconditioned jump instructions

OF DF IF TF SF ZF AF PF CFJMP adr Jump

(unconditioned)

Formal semantic description (for different addressing modes):

a) Intersegment, absolute (direct) addressing jump:

JMP adr32 ; (CS) adr32h

(IP) adr32l .

Note that the complete address is contained in the instruction format! The semantic descriptioncould also be:

(CS) ((CS)0H+(IP)+4) ((CS)0H+(IP)+3)(IP) ((CS)0H+(IP)+2) ((CS)0H+(IP)+1).

b) Relative addressing jump:JMP disp8|disp16 ; (IP) (IP) + disp8|disp16

The displacement is contained in the instruction format.

c) Direct register addressing or indirect memory addressing (intra-segment) jump:JMP r16 | mem16 ; (IP) (r16) | (mem16) .

d) Indirect memory addressing jump (intersegment)

JMP mem32 ; (CS) (mem32)h

(IP) (mem32)l .


adr32 JMP ET-IN-ALT-SEG (CS) ((CS)0H+(IP)+4) ((CS)0H+(IP)+3)

(IP)

((CS)0H+(IP)+2)

((CS)

0H+(IP)+1)

disp16 JMP ET-IN-SEG (IP) (IP) +

+ ((CS)0H+(IP)+2) ((CS)0H+(IP)+1)

disp8 JMP FOARTE-APROAPE (IP) (IP) + ((CS)0H+(IP)+1)

r16 JMP BX (IP) (BX)

mem* JMP [BX] (IP) ((DS)0H+(BX)+1) ((DS)0H+(BX))

mem** JMP [DI] (CS) ((DS)0H+(DI)+3) ((DS)0H+(DI)+2)

(IP) ((DS)0H+(DI)+1) ((DS)0H+(DI))

* indirect addressing jump defined by an assembler directive as an intra-segment jump;** indirect addressing jump defined by an assembler directive as an intersegment jump.


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3. The arithmetic operations and their particularitiesThe microprocessor is an automat that executes predefined operations and doesnt understand the

semantic of the programs. This semantic and the operands and results significance have to be known,understood and handled correctly by the programmer. This is the reason you should:

understand and correctly handle the way numbers are stored in memory: signed or unsigned

integers, packed ZCB, ASCII, fixed point; estimate the size of the operands and the results and choose the necessary number of memory

locations in order to store them correctly;

understand the way the flags are being modified by these instructions.

4. Recommended workflowIn order to better understand the functionality of each instruction presented in the previous chapters four

programs will be presented:

The first program exemplifies logical and arithmetic instructions.

The second program exemplifies the conditioned and unconditioned jumps.

The third program and the fourth program approach a specific problem (presented in the appendixes).

You should write and assemble each program and then run it step by step using the disassembler tool(AFD) noting, at each step, the processor status and its modifications.Note that the numbers that appear at the start of each source code line are not part of the programs.

They are only used to identify each source code line.

5. Exercises5.1 Launch TASMB and edit (E) the source file given in Appendix 1.

5.2 Save (W) the source file as P2_1.asm and assemble it (dont forget to enable the assembler options).5.3 Display the symbols list (S command) and write down the address of each symbol.

5.4 Quit TASMB.5.5 Launch AFD and load the program using the L command (L P2_1.com).

5.6 Execute the program, step by step (F2), and note the modifications of the involved registers andmemory locations (as indicated din Appendix 1).

5.7 Repeat exercises 5.1 to 5.6 for the other three programs (given in Appendix 2, 3 and 4).


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6. Appendixes

6.1 Appendix 1 P3_1.asm source code

Please note the manner in which the flags are being modified by every instruction and verify yourfindings and observations with the examples given in the instruction summary.

org 100hmov ax,cs

mov ds,ax

conv: mov al,opb1

mov bl,opb2

xor ah,ah ;AH=0

xor bh,bh ;BH=0

cbw ;converts the byte stored in AL into

;a word by extending its sign bit (msb)

xchg ax,bx

cbw

compl: mov ax,bxneg bx ;2s complement

not ax ;logical NOT

;note that even if NEG and NOT are

;applied to the same values, their

;effect is different and this effect

;can be noticed in the final values

;stored in AX and BX

inc bx ;visualize BX and the memory location

dec opb2 ;with the address opb2

comp: xor cx,cx ;CF=0

cmp opw2,24h ;compare through subtraction: opw2-24h

test opw2,20h ;compare through logical AND:

;opw2 AND 20h

cmp opw2,23h ;the compare instructions are usually

;followed by conditioned jumps. thats

;the reason why the flags values are

;so important

cmp opw2,20h ;note the diff. between CMP and TEST

shifts: inc opb2

mov dx,opw1

mov cl,3

shl dx,1 ;logical shift left (1 position)

shl dx,cl ;logical shift left (3 positions)mov dl,opb1

shr dl,1 ;logical shift right (1 position)

sal dl,1 ;note the difference between

sar dl,1 ;logical shifts and arithmetic shifts

sar dl,cl

rotates: mov al,opb2

inc cl

rol al,1 ;note the difference between

ror al,1 ;shifts and rotations

xor si,si ;CF=0


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rcl al,1

rcr al,1 ;note the difference between

rcr al,cl ;simple rotations and the rotations

;using the carry flag (CF)

op_log: and al,00000010b ;please estimate the results and then

or al,10000000b ;verify them by executing the

;instructions

sum: mov bx,opw1 ;this instruction sequence simulates a

add bl,byte ptr opw2 ;16 bit addition through 8 bit

adc bh,byte ptr opw2+1

mov ax,bx ;additions. please estimate the result

daa ;in the two cases: signed operands and

;unsigned operands. note that the

;result is wrong before the DAA if the

;operands are considered unsigned. the

;result is correct only if the

;operands are considered signed

subs: mov dx,opw1 ;this sequence simulates a 16 bit

;subtraction through 8 bit subtractions

sub dl,low opw2 ;please estimate the result in the two

sbb dh,high opw2 ;cases (as specified for the addition)

mov ax,dx ;and verify if they are correct or not

das ;before the DAS instruction

mult: mov ax,opw1 ;note the difference between the result

mul opw2 ;obtained in (DX)|(AX) after the two

mov ax,opw1 ;multiply instructions.

imul opw2 ;write down the two results

aam

divide: mov ax,opw1 ;note the difference between the two

mov dx,0 ;division instructions by comparing

div opw2 ;the values obtained in AH and AL.

mov ax,opw2 ;note the need to write 0 in DX

and dx,0 ;before the division instruction

idiv opw1

int 20h

opw1: dw 0fffdh ;if regarded as an unsigned value: 65533

;if regarded as a signed value: -3

opw2: dw 23h ;35 (signed or unsigned value)opb1: db 0feh ;if regarded as an unsigned value: 254

;if regarded as a signed value: -2

opb2: db 23h ; 35 (signed or unsigned value)


17/19



Corneliu Burileanu

- 1 7 -


Please note that:

We usually declare any data at the end of the source code. If we want to declare them at the

beginning of the source code then the program should start with an unconditioned jump to thefirst instruction. Otherwise the processor will interpret the data declarations as instructions and

will try to execute them, the result being unpredictable. The following program exemplifies conditioned and unconditioned jumps and every conditioned

jump takes us to the instruction at label fin. This unconditioned, indirect jump takes us to theaddress stored in BX (back in the program at one of the labels adr1, adr2, adr3 or adr4).

This is the reason for which BX is modified before every conditioned jump.

org 100h

jmp start

op1: db 0feh ; if regarded as an unsigned value: 253

; if regarded as a signed value: -2

op2: db 3

start: mov ax,cs

mov ds,ax

; Conditioned jumps

mov al,op1

lea bx,adr1

cmp al,op2 ;please note the flags values and

;estimate the effect of the two

ja fin ;instructions: JA and JG.

;afterwards execute them and verify

adr1: jg fin ;your result

mov al,op2

lea bx,adr2

cmp al,op1 ;please note the flags values and;estimate the effect of the two

jb fin ;instructions: JL and JB.

;afterwards execute them and verify

adr2: jl fin ;your result

lea bx,adr3

cmp al,op2 ;please note the flags values and

jz fin ;estimate the effect of the three

adr3: lea bx,adr4 ;instructions: JZ, JNP and JP.

and al,0feh ;afterwards execute them and verify

jnp fin ;your result

adr4: jp fin

jmp exit ;unconditioned jumpfin: jmp bx ;indirect jump

exit: int 20h

end


18/19



Corneliu Burileanu

- 1 8 -


This program simulates a 16 bit multiplication using only 8 bit multiplications. The result is a 32 bitnumber and is stored in memory at the addresses hrez and lrez.

The algorithm is presented below:

A 16 bit number is represented as follows: XYZTh = XY * 256 + ZT (XY is the high byte and

ZT is the low byte). The product: ABCDh * XYZTh = AB*XY*256*256 + (AB*ZT + XY*CD)*256 + CD*ZT.

The multiplications with 256 are done by several shifts.

In the end the result is compared with the result of a direct 16 bit multiplication.

org 100h

start: mov al,byte ptr op1+1

mul byte ptr [op2+1]

mov hrez,ax

mov al,byte ptr op1+1

mul byte ptr op2

mov dx,axmov cl,8

sal ax,cl

mov cl,8

shr dx,cl

add lrez,ax

adc hrez,0

add hrez,dx

mov al,byte ptr op2+1

mul byte ptr op1

mov dx,ax

mov cl,8

shl ax,clmov cl,8

shr dx,cl

add lrez,ax

adc hrez,0

add hrez,dx

mov al,byte ptr op1

mul byte ptr op2

add lrez,ax

adc hrez,0

mov ax,lrez

mov dx,hrezmov ax,op1

mul op2

int 20h

op1: dw 300

op2: dw 200

lrez: dw ?

hrez: dw ?s

end


19/19



Corneliu Burileanu


Presume a 16 words string, called string, with identical elements (equal to a specified reference valuereference). The problem consists of identifying all the different elements of the string and specifying their

position in the string.The memory zone starting at address nodiff will store the elements which are not equal to the

reference value and the memory zone starting at position will store these elements positions in the string.

org 100h

mov ax, cs

mov ds, ax

lea di, string

cld

mov bx,0ffffh

mov ax, reference

mov cx, (nodiff-string)/2

label1: repz scasw

jz fin

inc bxmov dx,[di-2]

shl bx,1

mov [nodiff+bx], dx

mov dx,di

sub dx,2

mov [position+bx], dx

shr bx,1

jmp label1

fin: inc bx

int 20h

string dw 1,1,2,3,1,1,1,1,4,1,5,1,1,1,4,1

nodiff dw 16 dup (0ffffh)

position dw 16 dup (0ffffh)

reference equ 1

end

An2 Derivat.ro Arhitectura-microprocesoarelor AMP Lab3 Eng 36298

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