1
control
zero
salt
PC
Memorie instructiuni
Registri
4
S
S
Mux
Memorie date
Mux
date
Mux
ALU
adresa
cod
Registru #
Registru #
Registru #adresa
date
data 2
data 1
data
Structura pentru execuţie într-un ciclu
2
Little-endian şi Big-endian
3
0781516232431
15141312
111098
7654
3210
12
0
4
8
adresa
Big-endian order
adresa superioara
adresa inferioara
0781516232431
12131415
891011
4567
0123
12
0
4
8
adresa
Little-endian order
adresa superioara
adresa inferioara
Read register 1
Read register 2
Write register
5
5
5
Instruction memory
MUX0
1Instr[15:11]
Instr[15:0]
Instr[20:16]
Instr[25:21]
16Sign-
extend
Instr[5:0] spre control ALU
Instr[31:0]
Read address
de la PC
32
Spre ALU
32
32
Registers
Read data 1
Read data 2
Read register 1
Read register 2
Write register
Write data
32
RegWrite de la memoria
de date
Regiştri
4
Regiştri-detalii
5
r0
r1
r2
r3
r4
.
.
.
r31
32
32
32
5
5
Read register 1
Read register 2
Read data 1
Read data 2
Write Data
DEC
Write register
5
MUX 2
MUX 1
32
RegWrite
Multiplexor vectorial
6
8
2
MUX 4x8
SEL
A[7..0]
D[7..0]
C[7..0]
B[7..0]
Multiplexor vectorial - detalii
7
MU
X
4x8
MU
X
4x8
MU
X
4x8
MU
X
4x8
MU
X
4x8
MU
X
4x8
MU
X
4x8
MU
X
4x8
Y0 Y7Y6Y5Y4Y3Y2Y1
A0 A7A6A5A4A3A2A1B0 B7B6B5B4B3B2B1C0 C7C6C5C4C3C2C1D0 D7D6D5D4D3D2D1
S0
S1
Celulă ALU pe un bit
8
0
1
a
Ainv
0
1
b
Binv
+
0
2
1result
Cin
Cout
operation2
Celulă ALU pe un bit pentru MIPS
9
0
1
a
Ainv
0
1
b
Binv
+
0
2
1result
Cin
Cout
operation
3Less
2
Celulă ALU pentru MIPS (MSB)
10
0
1
a
Ainv
b
Binv
+
0
2
1Result
Cin Operation
3Less
Overflow detection
0
1
Overflow
Set
2[Op1 Op0]
Cin
ALU
0LessC
out
Result0
Cin
ALU
1LessC
out
Result1
Cin
ALU
2LessC
out
Result2
Cin
ALU
31Less
Result31
. . .
a0b0a31b31 a2b2 a1b1
Set
Overflow
Operation
Carryin
000
AinvertBinvert
Zero
ALU pentru MIPS
11
Comenzi ALU
12
Functia
AND
OR
adunare
scadereSet on less
than
Ainv Binv op1 op0
NOR
00 00
10 00
00 10
00 11
10 11
01 01
Legatura între instrucţiuni şi comenzi ALU
13
Opcode ALUopSemnificatie
instrInstr[5:0]
Operatie ALU
ComenziALU
LW 00 load ward xxxxxx adunare 0010
SW 00 store ward xxxxxx adunare 0010
BEQ 01 branch equal xxxxxx scadere 0110
ADD 10 add 10000 adunare 0010
SUB 10 subtract 100010 scadere 0110
AND 10 AND 10100 AND 0000
OR 10 OR 100101 OR 0001
SLT 10 Set on less than 101010 Set on
less than 0111
R type
Jtype
Load/store
Tabel de adevar pentru comenzi ALU
14
ALUOpALUop1 ALUop0
0 0x 11 x1 x1 x1 x
F5 F4 F1F2F3 F0
Instr [5:0]
x
Comenzi ALU
Ainv op0op1Binv
00xxxxx 01x 10xxxxx 01x 000000x 01x 100100x 01x 000010x 00x 001010x 10
1 x x 100101x 11
Extinderea formatului
15
011 10 9 8 7 6 5 4 3 2 1bs bs bs bs bs bs bs bs bs bs bs bs bs bs bs 14 13 12bs bs
Instr[15:0]
16
00011 10 9 8 7 6 5 4 3 2 1bs bs bs bs bs bs bs bs bs bs bs bs bs 14 13 12bs bs
Shift left 2
Sign-extended
Semnale de comandă
16
Nume semnal
Efectul la dezactivare Efectul la activare
RegDst Adresa registrului destinatie provine din campul instr[15:11]Adresa registrului destinatie provine din campul instr[20:16]
RegWrite Valoarea de la intrarea Data este scrisa in registrul selectatNu
ALUSrc Al II-lea operand ALU este Sign-extended Al II-lea operand ALU provine de la iesirea Read data 2
Branch Valoarea PC este inlocuita cu valoarea calculata pentru saltValoarea PC este cea calculata in faza de fetch
MemRead Este citita locatia selectata in Data memoryNu
MemWriteSe inscrie informatia de la intrarea Write data in locatia selectata in Data memory
Nu
MemtoRegLa intrarea Write Data este transmisa iesirea din blocul Data memory
La intrarea Write Data este transmisa iesirea ALU
Fluxul de date şi unitatea de control
17
PC
Memorie instructiuni
Registri
4
SS
Mux
Data memory
Mux
Write data
Mux
ALU
adresa
cod
Read register 1
Write register
Read register 2
Address
Write data
Read data 2
Read data 1
Read data
0
1
Instr[20:16]
Instr[25:21]
Instr[15:11]
ALU control
Mux
0
1
0
1
Zero
0
1
controlInstr[31:26]
Shift left 2
RegWrite
RegDst ALUSrc
ALUop
Sign-extend
4
2
MemWrite
MemtoReg
MemRead
Branch
Instr[15:0]
Instr[5:0]
Calea de date pentru o operaţie aritmetică
18
PC
Memorie instructiuni
Registri
4
SMux
Mux
Write data
Mux
ALU
adresa
cod
Read register 1
Write register
Read register 2
Read data 2
Read data 1
0
1
Instr[20:16]
Instr[25:21]
Instr[15:11]
ALU control
Mux
0
1
0
1
Zero
0
1
controlInstr[31:26]
RegWrite
RegDst ALUSrc
ALUop
4
2
MemtoReg
Branch
Instr[15:0]
Instr[5:0]
Calea de date pentru LW
19
PC
Memorie instructiuni
Registri
4
SMux
Data memory
Mux
Write data
Mux
ALU
adresa
cod
Read register 1
Write register
Read register 2
Address
Write data
Read data 2
Read data 1
Read data
0
1
Instr[20:16]
Instr[25:21]
ALU control
Mux
0
1
0
1
Zero
0
1
controlInstr[31:26]
RegWrite
RegDst ALUSrc
ALUop
Sign-extend
4
2
MemWrite
MemtoReg
MemRead
Branch
Instr[15:0]
20
PC
Memorie instructiuni
Registri
4
SS
Mux
Data memory
Write data
Mux
ALU
adresa
cod
Read register 1
Write register
Read register 2
Address
Write data
Read data 2
Read data 1
Read data
0
1
Instr[20:16]
Instr[25:21]
Instr[15:11]
ALU control
Mux
0
1
0
1
Zero
controlInstr[31:26]
Shift left 2
RegWrite
RegDst ALUSrc
ALUop
Sign-extend
4
2
MemWrite
MemtoReg
MemRead
Branch
Instr[15:0]
Instr[5:0]
Calea de date pentru SW
Calea de date pentru BEQ
PC
Memorie instructiuni
Registri
4
SS
Mux
Mux
ALU
adresa
cod
Read register 1
Read register 2
Read data 2
Read data 1
0
1
Instr[20:16]
Instr[25:21]
ALU control
0
1
Zero
controlInstr[31:26]
Shift left 2
RegWriteALUSrc
ALUop
Sign-extend
4
2
Branch
Instr[15:0]
Întrebări?
22
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