Intro Verilog

8/8/2019 Intro Verilog

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Verilog

Here, we will use the Verilog HDL

Used in academia and industry

VHDL is another common HDL

A lso used by both academia and industry

Many principles we will discuss apply to any HDL

Once you can think hardware, you should be able touse any HDL fairly quickly



History

Verilog was developed in 1984 by Philip Moorby.

It become property of Gateway Design Automation, which

was later acquired by Cadence design System.

In 1990 cadence released verilog to public. Open verilog international (OVI) was formed to control

language specifications.

In 1993 IEEE accepted OVI verilog as standard .

Verilog HDL is an IEEE standard -1364.

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Verilog Module

Module is the basic building block in Verilog.

Syntax : module module_name (port list );

port declarationParameter declaration A ssignments (data flow statement)Procedural blocksInstantiation of lower module

Tasks and functionendmodule



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Verilog Module

module decoder_2_to_4 (A, D) ;

input [1:0] A ;output [3:0] D ;

assign D = (A == 2'b00) ? 4'b0001 :(A == 2'b01) ? 4'b0010 :(A == 2'b10) ? 4'b0100 :(A == 2'b11) ? 4'b1000 ;

endmodule

Decoder 2-to-4

A[1:0]

D[3:0]

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4

ports namesof module

module name

port types

port sizes

modulecontents

keywords underlined



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Declaring A Module

Cant use keywords as module/port/signalnames .Choose a descriptive module name

Indicate the ports.

Declare the signals connected to the ports

Choose descriptive signal names

Declare any internal signals

Write the internals of the module (functionality)



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Declaring Ports Provides the interface by which module can

communicate with its environment.

Declare type of port input output inout (bidirectional)

Scalar (single bit) - dont specify a size

input cin;

Vector (multiple bits) - specify size using range Range is MSB to LSB (left to right) output [7:0] OUT;

input [0:4] IN;



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Module Port List

Multiple ways to declare the ports of a module

module Add_half(c_out, sum, a, b);

output sum, c_out;input a, b;«

endmodule

module Add_half(output c_out, sum,input a, b);

«

endmodule



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Module Port List

Multiple ways to declare the ports of a module

module xor_8bit(out, a, b);

output [7:0] out;input [7:0] a, b;

«

endmodule

module xor_8bit(output [7:0] out,input [7:0] a, b);

«

endmodule



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Module Styles

Modules can be specified different ways

Structural connect primitives and modules

RTL use continuous assignments

Behavioral use initial and always blocks

A single module can use more than one method!

What are the differences?



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Structural

A schematic in text form

Build up a circuit from gates/flip-flops

Gates are primitives (part of the language)

Flip-flops themselves described behaviorally

Structural design

Create module interface

Instantiate the gates in the circuit

Declare the internal wires needed to connect gates

Put the names of the wires in the correct port locations of the gates

For primitives, outputs always come first



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Structural Example

module majority (major, V1, V2, V3) ;

output major ;input V1, V2, V3 ;

wire N1, N2, N3;

and A 0 (N1, V1, V2),and A 1 (N2, V2, V3),and A 2 (N3, V3, V1);

or Or0 (major, N1, N2, N3);

endmodule

V1

V2

V2 V3

V3 V1

major

N1

N2

N3

A0

A1

A2

Or0

majority



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RTL Example

Module is specified by specify dataflow. The designer is aware to how the data flow

between register


output major ;input V1, V2, V3 ;

assign major = V1 & V2| V2 & V3| V1 & V3;

endmodule

V1

V2

V3

majormajority



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Behavioral Example Used to model behavior of design without concern of

hardware implementation details


output reg major ;input V1, V2, V3 ;

always @( V1, V2, V3) beginif (V1 && V2 || V2 && V3

|| V1 && V3)

major = 1;elsemajor = 0;

end

endmodule

V1

V2

V3

majormajority



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Language Conventions

Case-sensitivity

Verilog is case-sensitive.

K eywords are lower case

No space is allowed inside an indentifier. Different names must be used for different items within

the same scope

Identifier :

Upper and lower case alphabetical decimal digits

Underscore



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Language Conventions

Maximum of 1024 characters in identifier

First character not a digit

Statement terminated by ;

Strings enclosed in double quotes and must be on asingle line

Comments:

A ll characters after // in a line are treated as acomment

Multi-line comments begin with /* and end with */



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Four-Value Logic

A single bit can have one of FOUR values 0 Numeric 0, logical F ALSE

1 Numeric 1, logical TRUE

x Unknown or ambiguous value

z No value (high impedence)

Why x?

Could be a conflict, could be lack of initialization Why z?

Nothing driving the signal

Tri-states



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The x and z values

IN SIMULA TION

Can detect x or z using special comparison operators

x is useful to see:

Uninitialized signals

Conflicting drivers to a wire

Undefined behavior

IN RE ALITY

Cannot detect x or z

No actual x electrically just isnt 0, 1, or z

Except for some uninitialized signals, x is bad!

Multiple strong conflicting drivers => short circuit

Weak signals => circuit cant operate, unexpected results

z means nothing driving signal (tri-state)



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Resolving 4-Value Logic

A

B

OUT

A B OUT

0 0 0

0 1 1

1 1 1

0 x x

0 z x

1 x 1

1 z 1

A B OUT

0 0 0

0 1 0

1 1 1

0 x 0

0 z 0

1 x x

1 z x

A

B

OUT

AOUT A

OUT

0 1 x z

1 0 x x



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Representing Numbers R epresentation: <size>¶<base><number>

size => number of BITS (regardless of base used)

base => base the given number is specified in

number => the actual value in the given base

Size : Specified in decimal only and represents number of bitsin number

Can use different bases

Decimal (d or D) ± default if no base specified!

Hex (h or H)

Octal (o or O)

Binary (b or B)

Size defaults to at least 32«

You should specify the size explicitly!

Why create 32-bit register if you only need 5 bits?

May cause compilation errors on some compilers



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Number Examples

Number Decimal Equivalent A ctual Binary

4d3 3 0011

3h A 10 010

8o26 22 000101105b111 7 00111

8b0101_1101 93 01011101

8bx1101 - xxxx1101

o7 7 00000111(32 bits)

10 10 ????

Numbers with MSB of x or z extended with that value



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Review Questions

What are some advantages of using HDLs,instead of schematic capture?

What are some ways in which HDLs differ from

conventional programming languages? How arethey similar?

What are the different styles of Verilog coding?

Intro Verilog

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