An2 Derivat.ro Arhitectura-microprocesoarelor Cap6eng 48674

7/30/2019 An2 Derivat.ro Arhitectura-microprocesoarelor Cap6eng 48674

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© Microprocessor Architecture § 6

Corneliu BURILEANU

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6.1.6.1. Input/Output Device MapInput/Output Device Map

Port access:Port access:

a) As I/O ports:a) As I/O ports:

-- dedicated machine cyclesdedicated machine cycles

-- dedicated signals on control bus:dedicated signals on control bus: IORIOR andand IOWIOW

ININ d, portd, port

OUTOUT port, sport, s

-- dd is the implied accumulatoris the implied accumulator

-- port map is smaller than memory mapport map is smaller than memory map

-- restricted addressing modes for ports:restricted addressing modes for ports:

directdirect

register indirectregister indirect

Fast port accessFast port access

Dedicated instruction codesDedicated instruction codes

Dedicated pins on the control busDedicated pins on the control bus

6.6. INPUT/OUTPUT STRATEGIESINPUT/OUTPUT STRATEGIES




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b) Memory mapped I/Ob) Memory mapped I/O

-- the same machine cycles as for memory accessthe same machine cycles as for memory access

-- the same control signals as for memory access:the same control signals as for memory access: MEMRMEMR andand MEMWMEMW

All data transfer characteristics are available for I/O instructAll data transfer characteristics are available for I/O instruct ions, also.ions, also.

Data processing instructions use ports also (Data processing instructions use ports also (only CISC machinesonly CISC machines).).

Waste space in the memory map.Waste space in the memory map.

Long port access time (instruction formats, addressing modes).Long port access time (instruction formats, addressing modes).




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6.2. Typical Input/Output Techniques6.2. Typical Input/Output Techniques

Techniques able to synchronize the microcomputer with peripheralTechniques able to synchronize the microcomputer with peripheral equipments, through ports.equipments, through ports.

TechniquesTechniques A.A. Synchronized with current program.Synchronized with current program.

B.B. NotNot--synchronized with current program.synchronized with current program.

A.A. ““PollingPolling”” TechniqueTechnique




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Example:Example:

Start1:Start1: ININ AL, PORT1 AL, PORT1SHLSHL AL, 1 AL, 1

JNCJNC Start1Start1

OUTOUT PORT1, AXPORT1, AX

Start2:Start2: ININ AL, PORT2 AL, PORT2

SHLSHL Al, 1 Al, 1

JNCJNC Start2Start2OUTOUT PORT2, AXPORT2, AX

Advantages:Advantages:

-- No extra hardware.No extra hardware.

-- Synchronic communication with peripheral equipments.Synchronic communication with peripheral equipments.

Shortcomings:Shortcomings:

-- Polling is time consuming.Polling is time consuming.

-- Some communication requests could be lost.Some communication requests could be lost.




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B. InterruptsB. Interrupts

Interrupt requestInterrupt request: signal sent to a dedicated microprocessor used by a peripheral: signal sent to a dedicated microprocessor used by a peripheral equipment (through aequipment (through a

port) to ask system resources access.port) to ask system resources access.

Interrupt request responseInterrupt request response: a sequence of steps achieved by the microprocessor leaving the: a sequence of steps achieved by the microprocessor leaving the currentcurrentprogram.program.

Handler (interrupt service routine)Handler (interrupt service routine): a dedicated program, at a specified location, used to respond: a dedicated program, at a specified location, used to respond to anto an

interrupt request of a specified peripheral device.interrupt request of a specified peripheral device.




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Interrupt request response:Interrupt request response:

1. (SP)1. (SP)←←

(SP)(SP) -- 22((SP) + 1)((SP) + 1) ↑↑ ((SP))((SP)) ←← (F)(F)

2. (SP)2. (SP) ←← (SP)(SP) -- 22

((SP) + 1)((SP) + 1) ↑↑ ((SP))((SP)) ←← (PC)(PC)

3. for i = 1 to n do3. for i = 1 to n do

(SP)(SP) ←← (SP)(SP) -- 22

((SP) + 1)((SP) + 1) ↑↑ ((SP))((SP)) ←← (r16(r16ii))

4. IF4. IF ←← 00

5. (PC)5. (PC) ←← adr adr

6.6. when returns to the main programwhen returns to the main program – – retrieves all information from stack retrieves all information from stack

nn is the total number of involved registers.is the total number of involved registers.




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6.3. Interrupts for a General Purpose Microprocessor6.3. Interrupts for a General Purpose Microprocessor

a) Direct Memory Access (a) Direct Memory Access (DMADMA):):

-- maximum prioritymaximum priority

-- waits for current machine cycle endwaits for current machine cycle end




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b) Nonb) Non--maskablemaskable interrupts:interrupts:

-- Dedicated pin (Dedicated pin (““NMINMI””))

-- Cannot be ignoredCannot be ignored-- Priority: after DMAPriority: after DMA

-- Waits for current instruction endWaits for current instruction end

-- Typical interrupt request responseTypical interrupt request response

-- Handler starting at a predefined addressHandler starting at a predefined address

c)c) MaskableMaskable interrupts:interrupts:

-- Another dedicated pin (Another dedicated pin (““INTINT””))

-- User interrupt enable (interrupt enable flag / flags)User interrupt enable (interrupt enable flag / flags)

-- Last priorityLast priority

-- Waits for current instruction endWaits for current instruction end

-- Typical interrupt request responseTypical interrupt request response

-- Handler starting address:Handler starting address:•• ““0 mode0 mode”” – – address defined by the peripheral deviceaddress defined by the peripheral device

•• ““1 mode1 mode”” – – handler starting at a predefined addresshandler starting at a predefined address

•• ““2 mode2 mode”” – – interrupt vectorsinterrupt vectors




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Interrupt vectorsInterrupt vectors

Interrupt vectorInterrupt vector:: the complete address of an interrupt handlerthe complete address of an interrupt handler

A peripheral device send, indirect, an interrupt vector from anA peripheral device send, indirect, an interrupt vector from an interrupt vector table, choosing a specificinterrupt vector table, choosing a specific

handlerhandler

Indirect memory addressing with anIndirect memory addressing with an interrupt vector tableinterrupt vector table

Issues:Issues:

-- Interrupt vector length (Interrupt vector length (mm))

-- bit number sent by the peripheral device (bit number sent by the peripheral device (““typetype””)) -- nn

-- Interrupt vector table dimension:Interrupt vector table dimension: mm xx 22nn bytesbytes

-- Interrupt vector table position in the memory mapInterrupt vector table position in the memory map




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Example:Example:

Interrupt_vector Interrupt_vector = ((I)= ((I) ↑ tiptip ↑ 0 + 1)0 + 1) ↑ ((I)((I) ↑ tiptip ↑ 0)0)

Interrupt vector is 2 bytes longInterrupt vector is 2 bytes long

typetype is 7 bit longis 7 bit long

Interrupt vector table has 256BInterrupt vector table has 256B

Interrupt vector table position is at the user choiceInterrupt vector table position is at the user choice




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6.4.6.4. Interrupt System for x86 Intel Microprocessor (IAInterrupt System for x86 Intel Microprocessor (IA--32) in Real Mode32) in Real Mode

Interrupt vector is 4 bytes longInterrupt vector is 4 bytes long

typetype is 8 bit longis 8 bit long

Interrupt vector table has 1kBInterrupt vector table has 1kB

Interrupt vector table position is fixedInterrupt vector table position is fixed




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INTINT [tip][tip] ;; (SP)(SP) ← (SP)(SP) -- 22

((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP)) ← (F)(F)

(IF)(IF) ← 00

((TFTF)) ← 00(SP)(SP) ← (SP)(SP) -- 22

((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP)) ← (CS)(CS)

if if tiptip thenthen

(CS)(CS) ← (4(4 ∗ tip + 3)tip + 3) ↑ (4(4 ∗ tip + 2)tip + 2)

elseelse

(CS)(CS) ← (0000FH)(0000FH) ↑ (0000EH)(0000EH)(SP)(SP) ← (SP)(SP) -- 22

((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP)) ← (IP)(IP)

if if tiptip thenthen

(IP)(IP) ← (4(4 ∗ tip + 1)tip + 1) ↑ (4(4 ∗ tip)tip)

elseelse

(IP)(IP) ← (0000DH)(0000DH) ↑ (0000CH(0000CH)




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INTOINTO ;; if if (OF) = 1(OF) = 1 thenthen

(SP)(SP) ← (SP)(SP) -- 22((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP)) ← (F)(F)

(IF)(IF) ← 00

((TFTF)) ← 00

(SP)(SP) ← (SP)(SP) -- 22

((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP)) ← (CS)(CS)

(CS)(CS) ← (00013H)(00013H) ↑ (00012H)(00012H)

(SP)(SP) ← (SP)(SP) -- 22

((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP)) ← (IP)(IP)

(IP)(IP) ← (00011H)(00011H) ↑ (00010H)(00010H)

IRETIRET ;; (IP)(IP) ← ((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP))

(SP)(SP) ← (SP) + 2(SP) + 2

(CS)(CS) ← ((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP))

(SP)(SP) ← (SP) + 2(SP) + 2(F)(F) ← ((SS)((SS) ↑ 0H + (SP) +1)0H + (SP) +1) ↑ ((SS)((SS) ↑ 0H + (SP))0H + (SP))

(SP)(SP) ← (SP) + 2(SP) + 2




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_______________________________________________________________________________

InterruptInterrupt Interrupt vectorInterrupt vector Implied functionImplied function

typetype addressaddress

________________________________________________________________ ________________________________________________________________ ________________ ________________

00 00H00H ÷÷ 03H03H ““Divide by 0Divide by 0”” interrupt requestinterrupt request

11 04H04H ÷÷ 07H07H ““Step by stepStep by step”” interrupt requestinterrupt request

22 08H08H ÷÷ 0BH0BH HardHard interrupt requestinterrupt request

33 0CH0CH ÷÷ 0FH0FH Minimum formatMinimum format soft interruptsoft interrupt

44 10H10H ÷÷ 13H13H INTOINTO

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An2 Derivat.ro Arhitectura-microprocesoarelor Cap6eng 48674

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