ES210 Spring 2013 Lecture 5 Verilog

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    Verilog

    Section 3.10

    Section 4.5

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    Keywords

    Keywords are predefined lowercaseidentifiers that define the languageconstructs

    Key example of keywords: module,endmodule, input, output, and wire.

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    assign

    The assignment is said to be sensitive tothe variables in the RHS expressionbecause anytime a variable in the RHS

    changesduring the simulation, the RHSexpression is reevaluated and theresult is used to updatethe LHS.

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    Semicolon

    Each statement must end with asemicolon (;)

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    Bitwise Logic Operation

    Bitwise means 1 bit at a time

    Bitwise logic operator Verilog

    AND a&b

    OR a|b

    XOR a^b

    INVERT ~a

    NAND ~(a&b)

    NOR ~(a|b)

    XNOR !(a^b)

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    wire

    You can think of a wire as a wire in a

    circuit where actual voltagesCould be measured.

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    Wire example

    Use & for AND operationUse tilda (~) for the INVERT operationUse | for the OR operation

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    Waveform

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    Using Verilog Primitives

    Verilog also has keywords such as andorand not.

    The output of a primitivemust be listed first.

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    Gate Delays

    In Verilog, the propagation delay of agate is specified in terms of time unitsand is specified by the symbol #.

    `timescale 1ns/100ps

    The first number specifies the unit ofmeasurement for time delays.

    The second number specifies theprecisions for which the delays arerounded off.

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    Gate Delay

    E is not defined until after 1 ns.

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    Gate Delay

    E is not defined until 1 ns.W is not defined until 2 ns.This means that D is not defined until 3 ns.

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    Binary Addition Example

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    Derivation of (ES112 Slides)

    Question: What primitive best implements ?

    Inputs: A, B Outputs: = + =

    B A 0 0 0

    1 0 1

    0 1 1

    1 1 0

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    Derivation of Carry Out(ES112 Slides)

    Question: What primitive best implements Co?

    Inputs: A, B Outputs: Co=AB

    B A Co

    0 0 0

    1 0 0

    0 1 0

    1 1 1

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    Implementation of a Half-Adder

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    Limitation of a Half Adder

    A half-adder does notaccount for carry-in.

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    Truth Table for a Full Adder

    carry-in

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    Karnaugh Map For the Sum Bit(ES112 Review)

    = + + + = + + + = + + + = ( )

    K h M F th C O t Bit

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    Karnaugh Map For the Carry-Out Bit(ES112 Review)

    C = + + = +

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    Implementation of a Full Adder

    = +

    C = ( )(carry-in)

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    Schematic of a Full Adder

    Half-adder(not including the bubble)

    Half-adder

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    Build a Verilog Representation ofa Full Adder Circuit

    Build a half adder circuit

    Build a test bench for the adder circuit

    Assemble a full adder circuit Build a test bench circuit to test the full

    adder

    Write the code to implement theadder circuit on FPGA

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    Build a Half-Adder Circuit

    (Figure 4.5)

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    Build a Test Bench in Verilog

    Ideas: (page 112 of the textbook)1. reg2. Initial statement3. Assign value to a single bit4. $finish

    1b0=one binary digit with a value of 01b1=one binary digit with a value of 1

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    Initial, $finish

    inital: keyword used with a set ofstatements that begin executing whensimulation is initialized.

    $finish: specifies the termination ofsimulation.

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    Block statement

    A block statement consists of severalstatements that are executed in sequencefrom top to bottom.

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    Build a Full-Adder Circuit

    w1

    w2 w3

    M1 M2

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    Full-Adder Top Level Circuit

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    Build a FPGA Top Level Circuit

    (x) (y) (z) (s) (c)

    See gates2.pdf (available from the course website) for reference